Wednesday, February 19, 2014

Productivity and IE in Semiconductor and Related Device Manufacturing




2012
Manufacturing science solutions to increase equiPment ProductiVity and fab Performance
http://www.eniac-improve.eu/



Implementing manufacturing science solutions to
increase equipment productivity and fab performance
http://www.eniac.eu/web/downloads/projectprofiles/call1_eniac_improve.pdf


Semiconductor Manufacturing Equipment
USITC Publication 3868
June 2006
OFFICE OF INDUSTRIES U.S. International Trade Commission
Washington, DC 20436 UNITED STATE
http://www.usitc.gov/publications/332/pub3868.pdf

This report addresses  trade and industry conditions for semiconductor manufacturing equipment (SME)
for  2005.
• The U.S. SME industry is strongly competitive in most equipment and is one of the few
industries in which the United States has a substantial trade surplus ($7.1 billion in 2005).
U.S. manufacturers share worldwide production and technological leadership with European
and Japanese companies.
• The SME industry is dominated by the major top-tier firms. In 2004, the top 10 worldwide
SME companies accounted for almost 58 percent of total industry sales.  Research and development and marketing are extremely important to the
industry.
• The U.S. trade surplus in SME grew from $4.1 billion in 2001 to $7.1 billion in 2005. The
largest gains were made in bilateral trade with Taiwan, Korea, China, and Singapore. Most
countries involved in SME trade are signatories to the Information Technology Agreement,
which eliminated tariffs for SME.
• Semiconductor producers are the main consumers of SME. They need SME to outfit newly
constructed semiconductor fabrication facilities as well as to replace and upgrade existing
equipment. Taiwan, Korea, and Japan were the largest markets for U.S. SME in 2005. Asia
has grown as the major market for SME due in part to the increase in new fabrication facility
construction from 2001 through 2005.
• Three major long-term trends are driving equipment sales: (1) transition to larger silicon wafer
sizes (from 200 mm diameter wafers to 300 mm diameter wafers), allowing more surface area
on which to build chips, (2) the use of 0.09 and smaller-micron lithography to improve the
functionality of chips while reducing their size, and (3) the use of copper for interconnects
instead of aluminum because of its higher conductivity.
http://www.usitc.gov/publications/332/pub3868.pdf

Closed-Loop Measurement of Equipment Efficiency and Equipment Capacity
Robert C. Leachman
Dept. of Industrial Engineering and Operations Research
University of California at Berkeley
Berkeley, CA 94720-1777
January, 2002
http://www.ieor.berkeley.edu/~ieor130/OEE%20paper%20revised.pdf

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