https://www.renesas.com/us/en/blogs/semiconductor-process-technology-history-trends-and-evolution
https://www.tsmc.com/english/dedicatedFoundry/technology/logic
Intel Introducing New Technology in 2024
https://spectrum.ieee.org/intel-20a
2023
Machine Allocation in Semiconductor Wafer Fabrication Systems: A Simulation-Based Approach
Published: 08 March 2023
Volume 32, pages 372–390, (2023)
https://link.springer.com/article/10.1007/s11518-023-5558-8
https://www.researchgate.net/publication/282980962_Discrete-Event_Simulation_for_Semiconductor_Wafer_Fabrication_Facilities_A_Tutorial
Logic Technology
In 2022, TSMC led the foundry to start 3nm FinFET (N3) technology high volume production. TSMC’s 3nm process is the industry’s most advanced semiconductor technology offering best power, performance, and area (PPA), and is a full-node advance from its 5nm generation. Following N3 technology, TSMC introduced N3E and N3P, enhanced 3nm processes for better power, performance and density. TSMC will further expand its 3nm technology family to meet diverse customer demands. These include N3X, a process tailored for high performance computing (HPC) applications, and N3AE, enabling early start of automotive applications on the most advanced silicon technology. N3A technology will be qualified and ready in 2026.
2016
The Influence of Industrial Engineering in Semiconductor
Fabrication Factory Optimization
M.A. Chik
Silterra Malaysia Sdn. Bhd.,
Proceedings - International Conference on Industrial Engineering and Operations Management, Kuala Lumpur, Malaysia, March 8-10, 2016
2015
Discrete-Event Simulation for Semiconductor Wafer Fabrication Facilities: A Tutorial
October 2015The International Journal of Industrial Engineering: Theory, Applications and Practice 22(5):661-682
Authors:
J.W. Fowler
Arizona State University
Lars Mönch
FernUniversität in Hagen
Thomas Ponsignon
Infineon Technologies
2013
MICL Seminar
Inside Intel Logic Technology Development: Taking SRAM From 32nm Planar to 22nm Tri-gate Technology
Dr. Eric Karl
Design Engineer
Intel Corporation
Friday, February 1, 2013 @ 3:00 pm
Future electronic product applications demand increasing performance with reduced power consumption at a constant or shrinking cost, which motivates technology scaling that targets high-performance at reduced operating voltages. The electrical benefits of geometric shrinks in advanced process technologies have greatly diminished, and innovation in materials engineering, device architecture and circuit co-optimization are required to provide performance and power advantages in the future. The role of advanced circuit design teams in driving Intel technology development is highlighted, with a focus on memory circuits. Random and systematic device variations pose significant challenges to SRAM Vmin and low-voltage performance as technology scaling follows Moore's law to the 22nm node. A high-performance, voltage-scalable 162Mb
SRAM array in a 22nm tri-gate bulk technology featuring 3rd-generation high-k metal-gate transistors and 5th-generation strained silicon is discussed. Processcircuit co-optimization of write and read assist features addresses process variation and fin quantization at 22nm and enables a 175mV reduction in the supply voltage required for 2GHz SRAM operation.
Eric Karl is an Design Engineer in Intel's Logic Technology Development group located in Hillsboro, Oregon, where he is responsible for memory technology development for Intel's advanced logic processes. He joined Intel in 2008 and has been responsible for technology lead vehicle design, memory bitcell development and memory circuit technology pathfinding. Prior to joining Intel LTD,
he worked on circuit design at the IBM T. J. Watson Research Center, Intel Circuit Research Labs and Sun Microsystems. Dr. Karl is currently developing memory bitcells and circuit technology for Intel's 10nm logic technology. In 2012, he received an Intel Achievement Award for work on 22nm memory circuit technology.
Dr. Karl received BSE, MSE, and PhD degrees in Electrical Engineering from the University of Michigan "“ Ann Arbor in 2002, 2004, and 2008, respectively. He has authored or co-authored more than 15 technical papers and holds several patents.
https://micl.engin.umich.edu/event/inside-intel-logic-technology-development-taking-sram-from-32nm-planar-to-22nm-tri-gate-technology
A consistent approach for vehicle planning and control in large unified automated material handling systems
January 2006
Authors:
Jairo R. Montoya-Torres
Universidad de La Sabana
Stéphane Dauzère-Pérès
Mines Saint-Etienne
Leon Vermariën
STMicroelectronics
Ud. 18.1.2024, 11.1.2024
Pub. 6.1.2024
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